1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device includes a stacked plurality of semiconductor memory chips.
2. Description of Related Art
Storage capacities required to semiconductor memories such as a dynamic random access memory (DRAM) have been increasing year by year. To satisfy such a request, a semiconductor memory device called multi-chip package has recently been proposed in which a plurality of memory chips are stacked on each other. In a multi-chip package, wirings for connecting a memory chip with the package substrate need to be provided each memory chip. This makes it difficult to stack a large number of memory chips.
In view of this, there has recently been proposed a type of semiconductor device in which a plurality of memory chips having through silicon vias are stacked (see Japanese Patent Application Laid-Open Nos. 2002-305283 and 2003-110086). In such a type of semiconductor device, through silicon vias that are located in the same planar positions as seen in the stacking direction formed in the memory chips are electrically short-circuited to one another. This prevents the number of electrodes to be connected to the package substrate from increasing even if the number of stacked memory chips increases. It is therefore possible to stack a greater number of memory chips.
In such a semiconductor device of stacked type using through silicon vias, an address space may extend because of increasing a storage capacity. For example, a stack of eight memory chips may be handled as a large-capacity chip having an address space eight times that of a single memory chip. In such a case, the through silicon vias connected in common between the memory chips are used in a time sharing manner since different memory chips are selected by respective accesses. There occurs no data conflict on the through silicon vias.
An increase in storage capacity due to stacking may also be used to extend the data input/output width instead of address extension. For example, eight memory chips each having eight data input/output terminals can be stacked to implement a data input/output width of 64 bits. Such a semiconductor device may be handled as a single memory module.
When the data input/output width is extended, the memory chips need to transfer data via respective different through silicon vias since all the memory chips are selected for every access. In this case, the same address signal is supplied to all the memory chips. In a read operation, for example, read data supplied from memory banks located in the same planar positions as seen from the stacking direction therefore need to be distributed so as to supply the read data to different through silicon vias chip by chip. The read/write buses connected between the memory banks and the through silicon vias need to be provided in equal lengths with respect to each memory bank. Distributing the read data to different through silicon vias chip by chip therefore has the problem of not only increasing the number of read/write buses required but also increasing the wiring lengths significantly.